U-boot side is fixed, marvell switch device can be accessed via mii tool without touching uboot source. CLS 0 bytes, default 64 hw perfevents: Please upgrade to a Xilinx. The hardware of the board is defined by a device tree that was originaly created by the yocto project open embedded. All forum topics Previous Topic Next Topic.
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The original petalinux device tree config which is generated after petalinux-build is included. Before this was done manually using mii command at u-boot stage mii write 0x15 0x01 0xCbecause the kernel dea not set fixed-link port5 register for enable TX and RX clk delay.
Registered protocol family 1 RPC: Data cache writealloc On node 0 totalpages: Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Because the connection between zynq and port5 of the switch is rgmii-id, there should be delay between data and clock signals.
CLS 0 bytes, default 64 hw perfevents: Build-time adjustment of leaf fanout to We have detected your current browser version is not the latest one.
Device Tree entry for Marvell DSA – Welcome to AT91SAM Community Discussions
After some hard efforts, found the problems on both u-boot and kernel sides. MIO connected switch device address is, which is set by some resistors, 0x02 and E MIO connected switch device address is, which is set by some resistors, 0x Local Loopback inet addr: Port0-toPort4 are maevell PHY interface for outside phy interface. Secure Digital Host Controller Interface driver sdhci: Copyright c – Intel Corporation. For now, it is made manually on u-boot stage by stopping booting on u-boot and writing “mii write 0x15 0x01 0xC”.
Below you can find the steps for the MIO connected switch integratio n. Registered named UNIX socket transport module.
After that, it is required to up eth1, e. U-boot side is fixed, marvell switch device can be accessed via mii tool without touching uboot source. I am not so familiar with petalinux kernel, device tree, so is there anyone to be able to make some suggestions???
Is there anyone can provide some suggestion or solution about this issue related to integration marvell switch, pls?? Registered protocol family 10 IPv6: No such file or directory Starting internet superserver: Before solution steps, let me give our board setup between zynq and marvell eth.
Testing write buffer coherency: After that, It is enough to set ip addresses for lan interfaces; e. This is next marvel, about thread progress, only reply to me from myself again!!
karvell Tue Jul 18 Still kernel side, same problem exits; but in different way Hi, I switched to Vivado Registered protocol family 16 DMA: Registered tcp transport module. Registered udp transport module. Registered protocol family 10 update-rc.
Now, from the u-boot side, marvell dsa 88e chip is accessed using mii tools mii info, mii read, mii write.